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NXP Semiconductors /MIMXRT1021 /ENET /TGSR

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Interpret as TGSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TF0_0)TF0 0 (TF1_0)TF1 0 (TF2_0)TF2 0 (TF3_0)TF3

TF2=TF2_0, TF0=TF0_0, TF1=TF1_0, TF3=TF3_0

Description

Timer Global Status Register

Fields

TF0

Copy Of Timer Flag For Channel 0

0 (TF0_0): Timer Flag for Channel 0 is clear

1 (TF0_1): Timer Flag for Channel 0 is set
TF1

Copy Of Timer Flag For Channel 1

0 (TF1_0): Timer Flag for Channel 1 is clear

1 (TF1_1): Timer Flag for Channel 1 is set
TF2

Copy Of Timer Flag For Channel 2

0 (TF2_0): Timer Flag for Channel 2 is clear

1 (TF2_1): Timer Flag for Channel 2 is set
TF3

Copy Of Timer Flag For Channel 3

0 (TF3_0): Timer Flag for Channel 3 is clear

1 (TF3_1): Timer Flag for Channel 3 is set

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data